lock loop

study of the bypass switching strategy and phase lock loop technique for fully digital-controlled ups

一种UPS的数字化锁相及旁路检测和切换控制技术

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A improved I p I q detecting method is put forward. In order to select phase A fundamental positive sequence voltage, a voltage selected unit based on low pass filter is used to replace the phase lock loop of I p I q detecting method.

之后提出了一种改进的ip-iq检测法，在该检测法中用基于低通滤波的A相正序电压提取单元代替原ip-iq检测法中的锁相环，以提取A相正序电压。

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a frequency and phase lock loop for carrier recovery

用作载波恢复的锁频锁相环

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Study of Design Method for Charge Pump Phase Lock Loop

电荷泵锁相环设计方法研究

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The orthogonal analog phase lock loop is used to get the timing information of the impulse radio system and the multi-path component separation.

使用正交模拟锁相环路对无载波的脉冲无线电系统实现多径捕获和同步提取。

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a dither control method which tracks the drift of dither mechanism's nature frequency with a phase lock loop

用锁相环跟踪抖动机构自然频率的抖动控制方法

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accurate ip behavioral modeling of phase lock loop

一种精确的锁相环IP模块行为级建模

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application of phase lock loop ic to the design of a heart rate display and alarm circuit

应用锁相环IC设计心率显示报警电路

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Relational Digital Phase Lock Loop slot synchronizer for PPM Laser Communication System

PPM光通信相关式数字锁相环时隙同步器

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the conduction of special cable and special phase lock loop technology makes high signal more accurate;

特种的传导电缆和特殊的锁相环技术使高度信号更精准；

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a pixel clock is generated by phase lock loop with high stability;

该系统采用锁相的方式，产生高稳定的像素时钟；

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Timing Acquisition of Impulse Radio System with Orthogonal Analog Phase Lock Loop

脉冲无线电通信系统的正交锁相环路同步方法

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a new algorithm for random harmonic current detection based on ip-iq principle without phase lock loop in three phase four wire system

三相四线制任意次谐波电流的无锁相环ip-iq检测新方法

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Design of SDH/ SONET Tributary Clock Jitter Attenuation Digital Phase Lock Loop

SDH/SONET支路时钟抖动衰减数字锁相环设计

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the coupling visibilities(cv) of temperature sensor heads were measured with phase lock loop technique.

采用锁相环技术测试了各传感器的分光可见度随温度的变化关系。

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a time synchronization mechanism and algorithm based on phase lock loop

基于锁相环的时间同步机制与算法

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Frequency source finally choose the decimal points a VCO frequency and phase lock loop, again through the two times frequency output reached the final index signal.

频率源最后选用了小数分频和压控振荡器构成锁相环路，再通过二次倍频最终输出达到指标的信号。

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the design of digital phase lock loop for inverter based on fpga

基于FPGA的逆变器全数字锁相环设计

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DSP Based Design of Phase Lock Loop for Digital UPS

基于DSP的数字化UPS锁相设计

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a kind of accurate automatic gain control circuit based on phase lock loop

基于锁相环的精确自动增益控制电路

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design of rf modem based on double phase lock loop

基于双锁相环路的RF调制解调器设计

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First modular design the three-phase phase lock loop, which realizes functions of the phase discriminator, loop filter and NCO. With the top connections finished, the whole three-phase PLL design has completed.

首先对三相锁相环进行模块化设计，然后分别实现了鉴相器、环路滤波器和数控振荡器的功能，最后经过顶层连接，完成了整个三相锁相环的设计。

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realization of ip-iq method without phase lock loop in active filter

无锁相环ip-iq法在有源滤波器中的实现

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resolution of systematic design trouble with pld interior phase lock loop.

使用PLD内部锁相环解决系统设计难题。

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